HY5DU12822DFP-D43 Datasheet, PDF (5/29 Pages) Hynix Semiconductor – 512Mb DDR SDRAM

PIN DESCRIPTION
PIN
TYPE
CK, /CK
Input
CKE
Input
/CS
BA0, BA1
Input
Input
A0 ~ A12
Input
/RAS, /CAS, /
WE
DM
(LDM,UDM)
Input
Input
DQS
(LDQS,UDQS)
I/O
DQ
VDD/VSS
VDDQ/VSSQ
VREF
NC
I/O
Supply
Supply
Supply
NC
Rev 1.0 / May 2007
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HY5DU12822DF(P) / HY5DU121622DF(P)
DESCRIPTION
Clock: CK and /CK are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and negative
edge of /CK. Output (read) data is referenced to the crossings of CK and /CK
(both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock sig-
nals, and device input buffers and output drivers. Taking CKE LOW provides
PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or
ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for
POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchro-
nous for SELF REFRESH exit, and for output disable. CKE must be maintained
high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK
and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVC-
MOS LOW level after VDD is applied.
Chip Select: Enables or disables all inputs except CK, /CK, CKE, DQS and DM.
All commands are masked when CS is registered high. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the
command code.
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read,
Write or PRECHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands, and the col-
umn address and AUTO PRECHARGE bit for READ/WRITE commands, to select
one location out of the memory array in the respective bank. A10 is sampled
during a Precharge command to determine whether the PRECHARGE applies to
one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be pre-
charged, the bank is selected by BA0, BA1. The address inputs also provide the
op code during a MODE REGISTER SET command. BA0 and BA1 define which
mode register is loaded during the MODE REGISTER SET command (MRS or
EMRS).
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command
being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a WRITE
access. DM is sampled on both edges of DQS. Although DM pins are input only,
the DM loading matches the DQ and DQS loading. For the x16, LDM corre-
sponds to the data on DQ0-Q7; UDM corresponds to the data on DQ8-Q15.
Data Strobe: Output with read data, input with write data. Edge aligned with
read data, centered in write data. Used to capture write data. For the x16,
LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on
DQ8-Q15.
Data input / output pin: Data bus
Power supply for internal circuits and input buffers.
Power supply for output buffers for noise immunity.
Reference voltage for inputs for SSTL interface.
No connection.
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