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HY5DU12822DFP-D43 Datasheet, PDF (23/29 Pages) Hynix Semiconductor – 512Mb DDR SDRAM
1
HY5DU12822DF(P) / HY5DU121622DF(P)
- Continue
Parameter
DDR400B
Symbol
Min Max
Data-out high-impedance window
from CK,/CK10
tHZ -0.7 0.7
Data-out low-impedance window
from CK, /CK10
tLZ -0.7 0.7
Input Setup Time (fast slew
rate)14,16-18
tIS 0.6 -
Input Hold Time (fast slew
rate)14,16-18
tIH 0.6 -
Input Setup Time (slow slew
rate)15-18
tIS 0.7 -
Input Hold Time (slow slew
rate)15-18
tIH 0.7 -
Input Pulse Width17
tIPW 2.2 -
Write DQS High Level Width
tDQSH 0.35 -
Write DQS Low Level Width
tDQSL 0.35 -
Clock to First Rising edge of DQS-
In
tDQSS
0.72
1.25
DQS falling edge to CK setup time tDSS 0.2 -
DQS falling edge hold time from
CK
tDSH 0.2
-
DQ & DM input setup time25
tDS 0.4 -
DQ & DM input hold time25
tDH 0.4 -
DQ & DM Input Pulse Width17
tDIPW 1.75 -
Read DQS Preamble Time
tRPRE 0.9 1.1
Read DQS Postamble Time
tRPST 0.4 0.6
Write DQS Preamble Setup Time12 tWPRES 0
-
Write DQS Preamble Hold Time tWPREH 0.25 -
Write DQS Postamble Time11
tWPST 0.4 0.6
Mode Register Set Delay
tMRD 2
-
Exit Self Refresh to non-Read
command23
tXSNR 75
-
Exit Self Refresh to Read
command
tXSRD 200 -
Average Periodic Refresh
Interval13,25
tREFI -
7.8
DDR333
Min Max
DDR266A
Min Max
-0.7 0.7 -0.75 0.75
-0.7 0.7 -0.75 0.75
0.75 -
0.9
-
0.75 -
0.9
-
0.8
-
1.0
-
0.8
-
1.0
-
2.2
-
2.2
-
0.35 - 0.35 -
0.35 - 0.35 -
0.75 1.25 0.75 1.25
0.2
-
0.2
-
0.2
-
0.2
-
0.45 -
0.5
-
0.45 -
0.5
-
1.75 - 1.75 -
0.9 1.1 0.9 1.1
0.4 0.6 0.4 0.6
0
-
0
-
0.25 - 0.25 -
0.4 0.6 0.4 0.6
2
-
2
-
75
-
75
-
200 - 200 -
-
7.8
-
7.8
DDR266B
Min Max
-0.75 0.75
-0.75 0.75
0.9
-
0.9
-
1.0
-
1.0
-
2.2
-
0.35 -
0.35 -
0.75 1.25
0.2
-
0.2
-
0.5
-
0.5
-
1.75 -
0.9 1.1
0.4 0.6
0
-
0.25 -
0.4 0.6
2
-
75
-
200
-
-
7.8
DDR200
UNIT
Min Max
-0.8 0.8 ns
-0.8 0.8 ns
1.1
-
ns
1.1
-
ns
1.1
-
ns
1.1
-
ns
2.5
-
ns
0.35 - tCK
0.35 - tCK
0.75 1.25 tCK
0.2
- tCK
0.2
- tCK
0.6
-
ns
0.6
-
ns
2
-
ns
0.9 1.1 tCK
0.4 0.6 tCK
0
-
ns
0.25 - tCK
0.4 0.6 tCK
2
- tCK
80
-
ns
200
- tCK
-
7.8 us
Rev 1.0 / May 2007
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