HY5DU12822DFP-D43 Datasheet, PDF (13/29 Pages) Hynix Semiconductor – 512Mb DDR SDRAM

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HY5DU12822DF(P) / HY5DU121622DF(P)
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is issued by the
low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and
CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to
write the data in mode register. During the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until reset by another MRS command.
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
0
Operating Mode
CAS Latency
BT
Burst Length
BA0 MRS Type
0
MRS
1
EMRS
A6 A5 A4 CAS Latency
00 0
Reserved
00 1
Reserved
01 0
2
01 1
3
10 0
4
10 1
1.5
11 0
2.5
11 1
Reserved
A3 Burst Type
0 Sequential
1 Interleave
A12~A9 A8 A7 A6~A0
Operating Mode
0
0 0 Valid
Normal Operation
0
1 0 Valid Normal Operation/ Reset DLL
0
0 1 VS Vendor specific Test Mode
-
--
-
All other states reserved
Rev 1.0 / May 2007
Burst Length
A2 A1 A0
Sequential Interleave
0 0 0 Reserved
Reserved
001
2
2
010
4
4
011
8
8
1 0 0 Reserved
Reserved
1 0 1 Reserved
Reserved
1 1 0 Reserved
Reserved
1 1 1 Reserved
Reserved
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