HC2509C Datasheet, PDF (5/6 Pages) Hynix Semiconductor – Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

HC2509C
March 1999
Table 6. Switching Characteristics Over Recommended Ranges of Supply
Voltage and Operating Free-air Temperature.(CL=30pF) (see Figure1 and 2) =
Parameter From(Input) TO(Output)
tphase error ♣
(normalized)
tsk
66MHz < CLKIN↑<
100MHz
CLKIN↑ = 100MHz
Any Y of FBOUT
Jitter(pk-pk)
CLKIN > 66MHz
Duty Cycle
tr
CLKIN > 66MHz
tf
=These parameters are not production tested.
♣ Phase error does not include jitter.
FBIN↑
FBIN↑
Any Y or
FBOUT
Any Y or
FBOUT
Any Y or
FBOUT
Any Y or
FBOUT
Any Y or
FBOUT
Vcc = 3.3V
Vcc =
±0.165V
3.3V±0.3V Unit
Min Typ Max Min Typ Max
-150
-150
ps
-50
50
ps
200 ps
-100
100 ps
45
55 %
1.3 1.9 0.8
2.1 ns
1.7 2.5 1.2
2.7 _ns
Figure 1. Load Circuit and Voltage Waveforms
From Output Under Test
30pF
500§Ù
Load Circuit For Outputs
Input
tpd
50% V_cc
Output
0.4V
tr
2V
50% V_cc
tf
3V
2V
0.4V
0V
VOH
VOL
Voltage Waveforms
Propagation Delay Times
Notes: 1. All input pulses are supplied by generators having
the following characteristics: PRR ≤ 100MHz, Zo
=50Ω, tr =1.2ns, tf=1.2ns
2.The outputs are measured one at a time with one
transition per measurement.
5