HC2509C Datasheet, PDF (3/6 Pages) Hynix Semiconductor – Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

HC2509C
March 1999
Table 1. Pin Description
Pin
Name
CLK
FBIN
IG
2G
FBOUT
1Y(0:4)
2Y(0:3)
AVcc
AGND
Vcc
GND
Pin No. Type
Functional Description
24
I
Clock Input. CLK provides the reference signal to the internal PLL.
13
11
14
12
3,4,5,8,9
I
Feedback Input. FBIN provides the feedback signal to the internal PLL.
Output Bank Enable. When 1G is high, all outputs 1Y(0:4) are enabled.
I
When 1G is low, Outputs 1Y(0:4) are disabled to a logic-low state.
Output Bank Enable. When 2G is high, all outputs 2Y(0:3) are enabled.
I
When 2G is low, Outputs 2Y(0:3) are disabled to a logic-low state.
Feedback Output. FBOUT completes the feedback loop of the PLL by being
O
wired to FBIN.
Clock Outputs. These outputs provide low-skew copies of CLKIN. Each output
O
has an embedded series-damping resistor.
16,17,
20,21
23
1
Clock Outputs. These outputs provide low-skew copies of CLKIN. Each output
O
has an embedded series-damping resistor.
Power
Analog Power Supply. AVcc provides the power reference for the analog
circuitry. AVcc can be also used to bypass the PLL for the test purpose.
When AVcc is strapped to ground, PLL is bypassed and CLK is buffered directly
to the device outputs.
Ground Analog Ground. AGND provides the ground reference for the analog circuitry.
2,10,15,22 Power Power Supply
6,7,18,19 Ground Ground
Table 2. Absolute Maximum Ratings Over Operating Free-air Temperature
Range
Symbols
Parameter
Vcc
Supply Voltage Range
VI
Input Voltage Range
Vo
Voltage Range applied to any input in the high or
low state
IIK
Input Clamp Current
IOK
Output Clamp Current
Io
PMAX
Tstg
Continuous Output Current
Maximum Power Dissipaiton
Storage Temperature Range
Value
-0.5 to 4.6
-0.5 to 6.5
-0.5 to
Vcc+0.5
±50
±50
±50
0.7
-65 to 150
Unit Conditions
V
V
V
mA VI <0 or VI >0
mA
Vo<0 or Vo>
Vcc
mA Vo=0 to Vcc
W
°C
3