HY57V643220D Datasheet, PDF (4/13 Pages) Hynix Semiconductor – 4Banks x 512K x 32bits Synchronous DRAM

HY57V643220D(L/S)T(P) Series
4Banks x 512K x 32bits Synchronous DRAM
Pin FUNCTION DESCRIPTIONS
Pin
CLK
CKE
CS
BA0, BA1
A0 ~ A10
RAS, CAS, WE
DQM0~3
DQ0 ~ DQ31
VDD/VSS
VDDQ/VSSQ
NC
Pin Name
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/
Ground
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the
SDRAM on the rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write
mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Rev. 0.3 / Sep. 2004
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