HY57V643220D Datasheet, PDF (11/13 Pages) Hynix Semiconductor – 4Banks x 512K x 32bits Synchronous DRAM

HY57V643220D(L/S)T(P) Series
4Banks x 512K x 32bits Synchronous DRAM
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter
Sym-
bol
45
Min Max
5
Min Max
55
Min Max
6
Min Max
7
Unit Note
Min Max
RAS
Cycle Time
Operation
tRC
58.5 -
55
-
55
-
60
-
63
- ns
RAS
Cycle Time
Auto Refresh _{tRRC 58.5 - 55 - 55 - 60 - 63 - ns}
RAS to CAS Delay
tRCD 18 - 15 - 16.5 - 18 - 20 - ns
RAS Active Time
tRAS 40.5 100K 38.7 100K 38.7 100K 42 100K 42 100K ns
RAS Precharge Time
tRP
18 - 15 - 16.5 - 18 - 20 - ns
RAS to RAS Bank Active
Delay
tRRD 9 - 10 - 11 - 12 - 14 - ns
CAS to CAS Delay
tCCD 1 - 1 - 1 - 1 - 1 - CLK
Write Command to
Data-In Delay
tWTL 0 - 0 - 0 - 0 - 0 - CLK
Data-in to Precharge
Command
tDPL TBD - TBD - TBD - 1 - 1 - CLK
Data-In to Active Command tDAL
tDPL + tRP
DQM to Data-Out Hi-Z
tDQZ 2 - 2 - 2 - 2 - 2 - CLK
DQM to Data-In Mask
tDQM 0 - 0 - 0 - 0 - 0 - CLK
MRS to New Command
tMRD 2 - 2 - 2 - 2 - 2 - CLK
Precharge to
CAS
Latency=3
tPROZ3 3
-
3
-
3
-
3
-
3
- CLK
Data Output
High-Z
CAS
Latency=2
tPROZ2 -
-
2
-
2
-
2
-
2
- CLK
Power Down Exit Time
tDPE
1
-
1
-
1
-
1
-
1
- CLK
Self Refresh Exit Time
tSRE
1
-
1
-
1
-
1
-
1
- CLK 1
Refresh Time
tREF
- 64 - 64 - 64 - 64 - 64 ms
Note :
1. A new command can be given tRC after self refresh exit.
Rev. 0.3 / Sep. 2004
11