HY5DU28422BT Datasheet, PDF (3/33 Pages) Hynix Semiconductor – 128M-S DDR SDRAM

HY5DU28422B(L)T
HY5DU28822B(L)T
DESCRIPTION
PRELIMINARY
The Hynix HY5DU28422B(L)T and HY5DU28822B(L)T are a 134,217,728-bit CMOS Double Data Rate(DDR) Synchro-
nous DRAM, ideally suited for the main memory applications which requires large memory density and high band-
width.
The Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
• VDD, VDDQ = 2.5V +/- 0.2V
• All inputs and outputs are compatible with SSTL_2
interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
• On chip DLL align DQ and DQS transition with CK
transition
• DM mask write data-in at the both rising and falling
edges of the data strobe
• tRAS Lock-out function supported
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
• Programmable /CAS latency 2 and 2.5 supported
• Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
• Internal four bank operations with single pulsed
/RAS
• Auto refresh and self refresh supported
• 4096 refresh cycles / 64ms
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
• Full and Half strength driver option controlled by
EMRS
ORDERING INFORMATION
OPERATING FREQUENCY
Part No.
HY5DU28422B(L)T-X*
HY5DU28822B(L)T-X*
Configuration
32Mx4
16Mx8
PACKAGE
400mil
66pin
TSOP-II
* X means speed grade
Grade
-J
-M
-K
-H
-L
CL2
133MHz
133MHz
133MHz
100MHz
100MHz
CL2.5
166MHz
133MHz
133MHz
133MHz
125MHz
Remark
(CL-tRCD-tRP)
DDR333 (2.5-3-3)
DDR266 (2-2-2)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR200 (2-2-2)
Rev. 0.3/May. 02
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