HY5DU28422BT Datasheet, PDF (27/33 Pages) Hynix Semiconductor – 128M-S DDR SDRAM

Parameter
Input Hold Time (slow slew rate)
Input Pulse Width
Write DQS High Level Width
Write DQS Low Level Width
Clock to First Rising edge of DQS-In
Data-In Setup Time to DQS-In (DQ & DM)
Data-in Hold Time to DQS-In (DQ & DM)
DQ & DM Input Pulse Width
Read DQS Preamble Time
Read DQS Postamble Time
Write DQS Preamble Setup Time
Write DQS Preamble Hold Time
Write DQS Postamble Time
Mode Register Set Delay
Exit Self Refresh to Any Execute Command
Average Periodic Refresh Interval
HY5DU28422B(L)T
HY5DU28822B(L)T
Symbol
tIH
tIPW
tDQSH
tDQSL
tDQSS
tDS
tDH
tDIPW
tRPRE
tRPST
tWPRES
tWPREH
tWPST
tMRD
tXSC
tREFI
DDR333
Min
Max
0.8
-
2.2
0.35
-
0.35
-
0.75
1.25
0.45
-
0.45
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
15.6
DDR266(2-2-2)
Min
Max
1.0
-
2.2
0.35
-
0.35
-
0.72
1.28
0.5
-
0.5
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
15.6
Unit
Note
ns
2,4,5,6
ns
6
CK
CK
CK
ns 6,7, 11~13
ns 6,7, 11~13
ns
CK
CK
CK
CK
CK
CK
CK
8
us
Rev. 0.3/May. 02
27