HY5DU28422BT Datasheet, PDF (14/33 Pages) Hynix Semiconductor – 128M-S DDR SDRAM

HY5DU28422B(L)T
HY5DU28822B(L)T
CKE FUNCTION TRUTH TABLE
Current
State
CKEn-
1
CKEn
/CS
H
L
L
SELF
REFRESH¹
L
L
L
L
H
L
L
POWER
DOWN²
L
L
L
L
H
H
H
H
ALL BANKS
IDLE⁴
H
H
H
H
L
H
ANY STATE
OTHER
H
THAN
L
ABOVE
L
X
X
H
H
H
L
H
L
H
L
H
L
L
X
X
X
H
H
H
L
H
L
H
L
H
L
L
X
H
X
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
X
H
X
L
X
/RAS
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
L
X
H
H
H
L
L
X
X
X
X
X
/CAS
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
L
X
H
H
L
H
L
X
X
X
X
X
/WE
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
H
X
H
L
X
X
L
X
X
X
X
X
/ADD
Action
X
INVALID
X
Exit self refresh, enter idle after tSREX
X
Exit self refresh, enter idle after tSREX
X
ILLEGAL
X
ILLEGAL
X
ILLEGAL
X
NOP, continue self refresh
X
INVALID
X
Exit power down, enter idle
X
Exit power down, enter idle
X
ILLEGAL
X
ILLEGAL
X
ILLEGAL
X
NOP, continue power down mode
X
See operation command truth table
X
Enter self refresh
X
Exit power down
X
Exit power down
X
ILLEGAL
X
ILLEGAL
X
ILLEGAL
X
ILLEGAL
X
NOP
X
See operation command truth table
X
ILLEGAL⁵
X
INVALID
X
INVALID
Note :
When CKE=L, all DQ and DQS must be in Hi-Z state.
1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.
2. All command can be stored after 2 clocks from low to high transition of CKE.
3. Illegal if CLK is suspended or stopped during the power down mode.
4. Self refresh can be entered only from the all banks idle state.
5. Disabling CLK may cause malfunction of any bank which is in active state.
Rev. 0.3/May. 02
14