HY5DU28422BT Datasheet, PDF (28/33 Pages) Hynix Semiconductor – 128M-S DDR SDRAM

HY5DU28422B(L)T
HY5DU28822B(L)T
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
<DDR266A/B, DDR200>
Parameter
Symbol
DDR266A
Min
Max
Row Cycle Time
tRC
65
-
Auto Refresh Row Cycle Time
tRFC
75
-
Row Active Time
tRAS
45
120K
Active to Read with Auto Precharge Delay
tRAP
20
-
Row Address to Column Address Delay
tRCD
20
-
Row Active to Row Active Delay
tRRD
15
-
Column Address to Column Address Delay tCCD
1
-
Row Precharge Time
tRP
20
-
Write Recovery Time
tWR
15
-
Write to Read Command Delay
tWTR
1
-
Auto Precharge Write Recovery +
Precharge Time
(tWR/tCK)
tDAL
+
-
(tRP/tCK)
System Clock Cycle
Time
CL = 2.5
CL = 2
7.5
12
tCK
7.5
12
Clock High Level Width
tCH
0.45
0.55
Clock Low Level Width
tCL
0.45
0.55
Data-Out edge to Clock edge Skew
tAC
-0.75
0.75
DQS-Out edge to Clock edge Skew
tDQSCK -0.75
0.75
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.5
Data-Out hold time from DQS
tQH
tHP
-tQHS
-
Clock Half Period
tHP
min
(tCL,tCH)
-
Data Hold Skew Factor
tQHS
-
0.75
Valid Data Output Window
tDV
tQH-tDQSQ
Data-out high-impedance window from CK,
/CK
tHZ
-0.75
0.75
Data-out low-impedance window from CK,
tLZ
/CK
-0.75
0.75
DDR266B
DDR200
Min Max Min Max
65
-
70
-
75
-
80
-
45
120K
50
120k
20
-
20
-
20
-
20
-
15
-
15
-
1
-
1
-
20
-
20
-
15
-
15
-
1
-
1
-
(tWR/tCK)
(tWR/tCK)
+
-
+
-
(tRP/tCK)
(tRP/tCK)
7.5
12
8.0
12
10
12
10
12
0.45 0.55 0.45 0.55
0.45 0.55 0.45 0.55
-0.75 0.75 -0.8
0.8
-0.75 0.75 -0.8
0.8
-
0.5
-
0.6
tHP
-tQHS
-
tHP
-tQHS
-
min
(tCL,tCH)
-
min
(tCL,tCH)
-
-
0.75
-
0.75
tQH-tDQSQ
tQH-tDQSQ
-0.75 0.75 -0.8
0.8
-0.75 0.75 -0.8
0.8
Unit Note
ns
ns
ns
ns
16
ns
ns
CK
ns
ns
CK
CK 15
ns
ns
CK
CK
ns
ns
ns
ns 1, 10
ns 1,9
ns
10
ns
ns
17
ns
17
Rev. 0.3/May. 02
28