HY57V28820HCT-I Datasheet, PDF (3/11 Pages) Hynix Semiconductor – 4Banks x 4M x 8bits Synchronous DRAM

FUNCTIONAL BLOCK DIAGRAM
4Mbit x 4banks x 8 I/O Synchronous DRAM
HY57V28820HC(L)T-I
Self refresh logic
& timer
Internal Row
counter
CLK
CKE
CS
RAS
CAS
WE
DQM
Row active
Row
Pre
Decoders
refresh
Column
Active
Column
Pre
Decoders
4Mx8 Bank3
4Mx8 Bank 2
4Mx8 Bank 1
4Mx8 Bank 0
Memory
Cell
Array
Y decoders
DQ0
DQ1
DQ6
DQ7
Bank Select
Column Add
Counter
A0
Address
A1
Registers
Burst
Counter
A11
BA0
BA1
Mode Registers
CAS Latency
Data Out Control ^{Pipe Line Control}
Rev. 0.1/Jan. 01
3