HY57V28820HCT-I Datasheet, PDF (1/11 Pages) Hynix Semiconductor – 4Banks x 4M x 8bits Synchronous DRAM

HY57V28820HC(L)T-I
4Banks x 4M x 8bits Synchronous DRAM
DESCRIPTION
The Hynix HY57V28820HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the Mobile applica-
tions which require low power consumption and extended temperature range. f HY57V28820HC(L)T is organized as
4banks of 4,194,304x8.
HY57V28820HC(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and
outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply
• Auto refresh and self refresh
• All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm • Programmable Burst Length and Burst Type
of pin pitch
- 1, 2, 4, 8 or Full Page for Sequential Burst
• All inputs and outputs referenced to positive edge of
system clock
- 1, 2, 4 or 8 for Interleave Burst
• Data mask function by DQM
• Programmable CAS Latency ; 2, 3 Clocks
• Internal four banks operation
ORDERING INFORMATION
Part No.
HY57V28820HCT-6I
HY57V28820HCT-KI
HY57V28820HCT-HI
HY57V28820HCT-8I
HY57V28820HCT-PI
HY57V28820HCT-SI
HY57V28820HCLT-6I
HY57V28820HCLT-KI
HY57V28820HCLT-HI
HY57V28820HCLT-8I
HY57V28820HCLT-PI
HY57V28820HCLT-SI
Clock Frequency
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
Power Organization
Normal
4Banks x 4Mbits
x8
Low power
Interface
LVTTL
Package
400mil 54pin TSOP II
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/Jan. 02
1