HY57V281620HCT Datasheet, PDF (3/13 Pages) Hynix Semiconductor – 4 Banks x 2M x 16bits Synchronous DRAM

FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 16 I/O Synchronous DRAM
HY57V281620HC(L)T
Self refresh logic
& timer
Internal Row
counter
CLK
CKE
CS
RAS
CAS
WE
UDQM
LDQM
Row active
Row
Pre
Decoders
refresh
Column
Active
Column
Pre
Decoders
2Mx16 Bank 3
2Mx16 Bank 2
2Mx16 Bank 1
2Mx16 Bank 0
Memory
Cell
Array
Y decoders
DQ0
DQ1
DQ14
DQ15
Bank Select
Column Add
Counter
A0
Address
A1
Registers
Burst
Counter
A11
BA0
BA1
Mode Registers
CAS Latency
Data Out Control ^{Pipe Line Control}
Rev. 0.2/Aug. 01
4