HY57V281620HCT Datasheet, PDF (2/13 Pages) Hynix Semiconductor – 4 Banks x 2M x 16bits Synchronous DRAM

PIN CONFIGURATION
PIN DESCRIPTION
HY57V281620HC(L)T
VDD 1
54 VSS
DQ0 2
53 DQ15
VDDQ 3
52 VSSQ
DQ1 4
51 DQ14
DQ2 5
50 DQ13
VSSQ 6
49 VDDQ
DQ3 7
48 DQ12
DQ4 8
47 DQ11
VDDQ 9
46 VSSQ
DQ5 10
45 DQ10
DQ6 11
44 DQ9
VSSQ 12
43 VDDQ
DQ7 13 54pin TSOP II 42 DQ8
VDD 14 400mil x 875mil 41 VSS
LDQM 15 ^{0.8mm pin pitch} 40 NC
/WE 16
39 UDQM
/CAS 17
38 CLK
/RAS 18
37 CKE
/CS 19
36 NC
BA0 20
35 A11
BA1 21
34 A9
A10/AP 22
33 A8
A0 23
32 A7
A1 24
31 A6
A2 25
30 A5
A3 26
29 A4
VDD 27
28 VSS
PIN
CLK
CKE
CS
BA0, BA1
A0 ~ A11
RAS, CAS, WE
UDQM, LDQM
DQ0 ~ DQ15
VDD/VSS
VDDQ/VSSQ
NC
PIN NAME
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe, Col-
umn Address Strobe, Write
Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE, UDQM and LDQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
RAS, CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Rev. 0.2/Aug. 01
3