HY57V281620HCT Datasheet, PDF (12/13 Pages) Hynix Semiconductor – 4 Banks x 2M x 16bits Synchronous DRAM

COMMAND TRUTH TABLE
HY57V281620HC(L)T
Command
Mode Register Set
CKEn-1 CKEn
H
X
No Operation
H
X
Bank Active
H
X
Read
H
X
Read with Autoprecharge
Write
H
X
Write with Autoprecharge
Precharge All Banks
H
X
Precharge selected Bank
Burst Stop
H
X
DQM
H
Auto Refresh
H
H
Burst-Read-Single-
WRITE
H
X
Entry
H
L
Self Refresh¹
Exit
L
H
Entry
H
L
Precharge
power down
Exit
L
H
Clock
Suspend
Entry
H
L
Exit
L
H
CS
RAS CAS
WE
DQM ADDR
A10/
AP
BA
L
L
L
L
X
OP code
H
X
X
X
X
X
L
H
H
H
L
L
H
H
X
RA
V
L
L
H
L
H
X
CA
V
H
L
L
H
L
L
X
CA
V
H
H
X
L
L
H
L
X
X
L
V
L
H
H
L
X
X
X
V
X
L
L
L
H
X
X
A9 Pin High
L
L
L
L
X
(Other Pins OP code)
L
L
L
H
X
H
X
X
X
X
X
L
H
H
H
H
X
X
X
X
L
H
H
H
X
H
X
X
X
X
L
H
H
H
H
X
X
X
X
L
V
V
V
X
X
X
Note
MRS
Mode
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
3. The burst read sigle write mode is entered by programming the write burst mode bit (A9) in the mode register to a logic 1.
Rev. 0.2/Aug. 01
13