HY5S7B6ALFP-6 Datasheet, PDF (27/52 Pages) Hynix Semiconductor – 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O

11
512Mbit (32Mx16bit) Mobile SDR Memory
HY5S7B6ALF(P) Series
READ
A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1)
cycle after read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address and
the bank select address at the read command set cycle. In a read operation, data output starts after the number of
clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the suc-
cessive burst-length data has been output.
The /CAS latency and burst length must be specified at the mode register.
tCK
CLK
Command
REA
D
DQ
Command
REA
D
DQ
NOP
NOP
tLZ
tOH
Do0
Do1
tAC
CL = 2
NOP
NOP
NOP
CL = 3
tLZ
tAC
tOH
Do0
Do2
Do3
Do1
Do2
Undefined
Do3
Don't Care
Read Burst Showing CAS Latency
Rev 1.1 / July. 2007
27