HY5PS1G431CFP Datasheet, PDF (27/37 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM

HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
Specific Notes for dedicated AC parameters
1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be
used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit
timing where a lower power value is defined by each vendor data sheet.
2. AL = Additive Latency
3. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and
tRAS(min) have been satisfied.
4. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency
5. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for other
slew rate values.
6. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0
V/ns. See System Derating for other slew rate values.
7. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS sig-
nals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single
ended mode. See System Derating for other slew rate values.
8. tDS and tDH derating
tDS, tDH Derating Values(ALL units in 'ps', Note 1 applies to entire Table)
DQ
Slew
rate
V/ns
DQS, DQS Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns 0.8 V/ns
△tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD
SHSHSHSHSHSHSHSHSH
2.0 125 45 125 45 +125 +45 - - - - - - - - - - - -
1.5 83 21 83 21 +83 +21 95 33 - - - - - - - - - -
1.0 0 0 0 0 0 0 12 12 24 24 - - - - - - - -
0.9 - - -11 -14 -11 -14 1 -2 13 10 25 22 - - - - - -
0.8 - - - - -25 -31 -13 -19 -1 -7 11 5 23 17 - - - -
0.7 - - - - -43 -54 -31 -42 -42 -19 -7 -8 5 -6 17 6 - -
0.6 - - - - -67 -83 - - -43 -59 -31 -47 -19 -35 -7 -23 5 -11
0.5 - - - - -110 -125 - - - - -74 -89 -62 -77 -50 -65 -38 -53
0.4 - - - - -175 -188 - - - - - - -127 -140 -115 -128 -103 -116
1) For all input signals the total tDS(setup time) and tDH(hold time) required is calculated by adding the datasheet value to the derating
value listed in Table x.
Setup(tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing
of Vih(ac)min. Setup(tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the
first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘ VREF(dc) to ac region’,
use nominal slew rate for derating value(see Fig a.) If the actual signal is later than the nominal slew rate line anywhere between shaded
‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value(see Fig b.)
Hold(tDH) nominal slew rate for a rising signal is defined as the slew ρατε between the last crossing of Vil(dc) max and the first crossing
of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc) min and the
first crossing of VREF(dc). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to VREF(dc) region’,
the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see Fig d.)
Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the time
of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Rev. 0.2 /Dec 2006
27