HY5PS1G431CFP Datasheet, PDF (12/37 Pages) Hynix Semiconductor – 1Gb DDR2 SDRAM

HY5PS1G431C(L)FP
HY5PS1G831C(L)FP
HY5PS1G1631C(L)FP
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
Symbol
V_IH(dc)
V_IL(dc)
Parameter
dc input logic high
dc input logic low
3.2.2 Input AC Logic Level
Min.
VREF + 0.125
- 0.3
Max.
VDDQ + 0.3
VREF - 0.125
Units
V
V
Symbol
V_IH (ac)
V_IL (ac)
Parameter
ac input logic high
ac input logic low
DDR2 400,533
DDR2 667,800
Min.
VREF + 0.250
Max.
-
Min.
VREF + 0.200
Max.
-
-
VREF - 0.250
-
VREF - 0.200
3.2.3 AC Input Test Conditions
Units
V
V
Notes
Notes
Symbol
V_REF
V_SWING(MAX)
SLEW
Condition
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
Value
0.5 * V_DDQ
1.0
1.0
Units
V
V
V/ns
Notes
1
1
2, 3
Note:
1. Input waveform timing is referenced to the input signal crossing through the V_REF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from V_REF to V_IH(ac) min for rising
edges and the range from V_REF to V_IL(ac) max for falling edges as shown in the figure below.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
V_SWING(MAX)
delta TF
delta TR
V_DDQ
V_IH(ac) min
V_IH(dc) min
V_REF
V_IL(dc) max
V_IL(ac) max
V_SS
Falling Slew = ^{VREF - VIL(ac) max}
delta TF
Rising Slew = ^{VIH(ac) min - VREF}
delta TR
< Figure : AC Input Test Signal Waveform>
Rev. 0.2 /Dec 2006
12