HY5S6B6D Datasheet, PDF (24/27 Pages) Hynix Semiconductor – 4Banks x1M x 16bits Synchronous DRAM

HY5S6B6D(L/S)F(P)-xE
4Banks x 1M x 16bits Synchronous DRAM
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter
RAS Cycle Time
RAS to CAS Delay
RAS Active Time
RAS Precharge Time
RAS to RAS Bank Active Delay
CAS to CAS Delay
Write Command to Data-In Delay
Data-in to Precharge Command
Data-In to Active Command
DQM to Data-Out Hi-Z
DQM to Data-In Mask
MRS to New Command
Precharge to Data Output
High-Z
CAS Latency=3
CAS Latency=2
Power Down Exit Time
Auto Refresh Cycle Time
Self Refresh Exit Time
Refresh Time
Symbol
tRC
tRCD
tRAS
tRP
tRRD
tCCD
tWTL
tDPL
tDAL
tDQZ
tDQM
tMRD
tPROZ3
tPROZ2
tDPE
tARFC
tSRE
tREF
S
B
Min Max Min Max
90
-
90
-
28.5
-
30
-
60 100K 60 100K
28.5
-
30
-
19
-
30
-
1
-
1
-
0
-
0
-
2
-
2
-
tDPL+tRP
2
-
2
-
0
-
0
-
2
-
2
-
3
-
3
-
2
2
1
-
1
-
90
105
1
-
1
-
-
64
-
64
Unit
ns
ns
ns
ns
ns
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
ns
CLK
ms
Note
1
Note : 1. A new command can be given tRC after self refresh exit.
Rev 0.3 / July 2004
24