HY5S6B6D Datasheet, PDF (10/27 Pages) Hynix Semiconductor – 4Banks x1M x 16bits Synchronous DRAM

HY5S6B6D(L/S)F(P)-xE
4Banks x 1M x 16bits Synchronous DRAM
COMMAND TRUTH TABLE
Function
CKEn-1 CKEn CS
Mode Register Set
H
Extended Mode Register Set
H
No Operation
H
Device Deselect
H
Bank Active
H
Read
H
Read with Autoprecharge
H
Write
H
Write with Autoprecharge
H
Precharge All Banks
H
Precharge selected Bank
H
Burst stop
H
Auto Refresh
H
Self Refresh Entry
H
Self Refresh Exit
L
Precharge Power Down Entry H
Precharge Power Down Exit
L
Clock Suspend Entry
H
Clock Suspend Exit
L
Deep Power Down Entry
H
Deep Power Down Exit
L
X
L
X
L
X
L
X
H
X
L
X
L
X
L
X
L
X
L
X
L
X
L
X
L
H
L
L
L
H
H
L
H
L
L
H
H
L
H
L
L
H
L
L
H
RAS CAS
L
L
L
L
H
H
X
X
L
H
H
L
H
L
H
L
H
L
L
H
L
H
H
H
L
L
L
L
X
X
H
H
X
X
H
H
X
X
H
H
X
X
V
V
X
H
H
X
WE
ADDR
A10/
AP
BA
0,1
Note
L
OP CODE
2
L
OP CODE
2
H
X
X
X
H
Row Address
V
H Column L
V
H Column H
V
L Column L
V
L Column H
V
L
X
H
X
L
X
L
V
L
X
H
X
H
X
X
X
1
H
X
X
H
X
X
H
X
X
V
X
L
X
X
Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.
2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set.
Rev 0.3 / July 2004
10