HY57V161610D Datasheet, PDF (2/13 Pages) Hynix Semiconductor – 2 Banks x 512K x 16 Bit Synchronous DRAM

PIN CONFIGURATION
V DD 1
DQ0 2
DQ1 3
V SSQ 4
DQ2 5
DQ3 6
V DDQ 7
DQ4 8
DQ5 9
V SSQ 10
DQ6 11
DQ7 12
VDDQ ¹³
LDQM ¹⁴
/WE ¹⁵
/CAS ¹⁶
/RAS ¹⁷
/CS ¹⁸
A11 ¹⁹
A10 ²⁰
A0 ²¹
A1 ²²
A2 ²³
A3 ²⁴
V DD
25
50pin TSOP II
400mil x 825mil
0.8mm pin pitch
HY57V161610D
50
VSS
49
DQ15
48
DQ14
47
VSSQ
46
DQ13
45
DQ12
44
VDDQ
43
DQ11
42
DQ10
41
VSSQ
40
DQ9
39
DQ8
38
VDDQ
37
NC
36
UDQM
35
CLK
34
CKE
33
NC
32
A9
31
A8
30
A7
29
A6
28
A5
27
A4
26
VSS
PIN DESCRIPTION
PIN
CLK
CKE
CS
BA
A0 ~ A10
RAS, CAS, WE
LDQM, UDQM
DQ0 ~ DQ15
VDD/VSS
VDDQ/VSSQ
NC
PIN NAME
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe, Write
Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
DESCRIPTION
The system clock input. All other inputs are referenced to the SDRAM on the rising
edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be one of the
states among power down, suspend or self refresh.
Command input enable or mask except CLK, CKE and DQM
Select either one of banks during both RAS and CAS activity.
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and WE define the operation.
Refer function truth table for details
DQM control output buffer in read mode and mask input data in write mode
Multiplexed data input / output pin
Power supply for internal circuit and input buffer
Power supply for DQ
No connection
Rev. 4.0/Aug. 02
2