HY57V161610D Datasheet, PDF (12/13 Pages) Hynix Semiconductor – 2 Banks x 512K x 16 Bit Synchronous DRAM

HY57V161610D
COMMAND TRUTH TABLE
Command
Mode Register Set
No Operation
Bank Active
Read
Read with Auto precharge
Write
Write with Auto precharge
Precharge All Bank
Precharge selected Bank
Burst Stop
U/LDQM
Auto Refresh
Burst-READ-Single-WRITE
Self Refresh¹
Entry
Exit
Precharge power
down
Entry
Exit
Clock Suspend
Entry
Exit
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM A0~A9
A10/
AP
BA
H
X
L
L
L
L
X
OP code
H
X
X
X
H
X
X
X
L
H
H
H
H
X
L
L
H
H
X
Row Address
V
H
X
L
H
L
H
X
Column
Address
L
H
V
H
X
L
H
L
L
X
Column
Address
L
H
V
H
X
H
X
L
L
H
L
X
X
L
V
H
X
L
H
H
L
X
X
H
X
V
X
H
H
L
L
L
H
X
X
H
X
L
L
L
L
X
A9 Pin High
(Other Pins OP code)
H
L
L
L
L
H
X
H
X
X
X
X
L
H
X
L
H
H
H
H
X
X
X
H
L
X
L
H
H
H
X
H
X
X
X
L
H
X
L
H
H
H
H
X
X
X
H
L
X
L
V
V
V
X
L
H
X
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high.
2. X=Do not care, L=Low, H=High, BA=Bank Address, RA= Row Address, CA=Column Address, Opcode=Operand Code,
NOP=No Operation.
Note
Rev. 4.0/Aug. 02
12