HYMD512G726B4-M Datasheet, PDF (15/16 Pages) Hynix Semiconductor – Low Profile Registered DDR SDRAM DIMM

SERIAL PRESENCE DETECT
HYMD512G726B(L)4M-M/K/H/L
Byte
Function Description
Function Supported
-M
-K
-H
-L
Hexa Value
-M
-K
-H
Note
-L
0
Number of Bytes written into serial memory at module
manufacturer
128 Bytes
80h
1 Total number of Bytes in SPD device
256 Bytes
08h
2 Fundamental memory type
DDR SDRAM
07h
3 Number of row address on this assembly
13
0Dh
1
4 Number of column address on this assembly
12
0Ch
1
5 Number of physical banks on DIMM
1Bank
01h
6 Module data width
72 Bits
48h
7 Module data width (continued)
-
00h
8 Module voltage Interface levels(VDDQ)
SSTL 2.5V
04h
9 DDR SDRAM cycle time at CAS Latency=2.5(tCK)
7.5ns
7.5ns
7.5ns
8ns
75h 75h 75h 80h 2
10 DDR SDRAM access time from clock at CL=2.5 (tAC) +/-0.75ns +/-0.75ns +/-0.75ns +/-0.8ns 75h 75h 75h 80h 2
11 Module configuration type
ECC
02h
12 Refresh rate and type
7.8us & Self refresh
82h
13 Primary DDR SDRAM width
x4
04h
14 Error checking DDR SDRAM data width
x4
04h
15 Minimum clock delay for back-to-back random column
address(tCCD)
1 CLK
01h
16 Burst lengths supported
2,4,8
0Eh
17 Number of banks on each DDR SDRAM
4 Banks
04h
18 CAS latency supported
2, 2.5
0Ch
19 CS latency
0
01h
20 WE latency
1
02h
21 DDR SDRAM module attributes
Registered, PLL
26h
+/-0.2Voltage tolerance,
22 DDR SDRAM device attributes : General
Concurrent Auto Precharge
C0h
tRAS Lock Out
23 DDR SDRAM cycle time at CL=2.0(tCK)
7.5ns
7.5ns
10ns
10ns
75h 75h A0h A0h 2
24 DDR SDRAM access time from clock at CL=2.0(tAC) +/-0.75ns +/-0.75ns +/-0.75ns +/-0.8ns 75h 75h 75h 80h 2
25 DDR SDRAM cycle time at CL=1.5(tCK)
-
00h
2
26 DDR SDRAM access time from clock at CL=1.5(tAC)
-
00h
2
27 Minimum row precharge time(tRP)
15ns
20ns
20ns
20ns
3Ch 50h 50h 50h
28 Minimum row activate to row active delay(tRRD)
15ns
15ns
15ns
15ns
3Ch 3Ch 3Ch 3Ch
29 Minimum RAS to CAS delay(tRCD)
15ns
20ns
20ns
20ns
3Ch 50h 50h 50h
30 Minimum active to precharge time(tRAS)
45ns
45ns
45ns
50ns
2Dh 2Dh 2Dh 32h
31 Module row density
1GB
01h
32 Command and address signal input setup time(tIS)
0.9ns
0.9ns
0.9ns
1.1ns
90h 90h 90h B0h
33 Command and address signal input hold time(tIH)
0.9ns
0.9ns
0.9ns
1.1ns
90h 90h 90h B0h
34 Data signal input setup time(tDS)
0.5ns
0.5ns
0.5ns
0.6ns
50h 50h 50h 60h
35 Data signal input hold time(tDH)
0.5ns
0.5ns
0.5ns
0.6ns
50h 50h 50h 60h
36~40 Reserved for VCSDRAM
Undefined
00h
41 Minimum active / auto-refresh time ( tRC)
60ns
65ns
65ns
70ns
3Ch 41h 41h 46h
42
Minimum auto-refresh to active/auto-refresh
command period(tRFC)
75ns
75ns
75ns
80ns
4Bh 4Bh 4Bh 50h
43 Maximum cycle time (tCK max)
12ns
12ns
12ns
12ns
30h 30h 30h 30h
44 Maximim DQS-DQ skew time(tDQSQ)
0.5ns
0.5ns
0.5ns
0.6ns
32h 32h 32h 3Ch
45 Maximum read data hold skew factor(tQHS)
46~61 Superset information(may be used in future)
62 SPD Revision code
63 Checksum for Bytes 0~62
0.75ns 0.75ns 0.75ns 0.75ns 75h 75h 75h 75h
Undefined
Initial release
-
00h
00h
5Dh 8Ah B5h 4Fh
Rev. 0.1 / June 2004
15