HYMD512G726B4-M Datasheet, PDF (10/16 Pages) Hynix Semiconductor – Low Profile Registered DDR SDRAM DIMM

HYMD512G726B(L)4M-M/K/H/L
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
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Bin Sort :M(DDR266(2-2-2),K(DDR266A@CL=2) H(DDR266B@CL=2.5),L(DDR200@CL=2)
Parameter
Symbol
-M
Min Max
-K
Min Max
H
Min Max
-L
Unit Note
Min Max
Input Setup Time (slow slew rate) tIS
1.0
-
1.0
-
1.0
-
1.1
- ns 2,4,5,6
Input Hold Time (slow slew rate)
tIH
1.0
-
1.0
-
1.0
-
1.1
- ns 2,4,5,6
Input Pulse Width
tIPW
2.2
-
2.2
-
2.2
-
2.5
- ns
6
Write DQS High Level Width
tDQSH 0.35
-
0.35
-
0.35
-
0.35
- CK
Write DQS Low Level Width
tDQSL 0.35
-
0.35
-
0.35
-
0.35
- CK
Clock to First Rising edge of DQS-In tDQSS 0.75 1.28 0.75 1.25 0.75
1.25
0.75
1.25 CK
Data-In Setup Time to DQS-In
(DQ & DM)
tDS
0.5
0.5
0.5
Data-in Hold Time to DQS-In
(DQ & DM)
tDH
0.5
0.5
0.5
0.6
ns
6,7,11~
13
0.6
ns
DQ & DM Input Pulse Width
tDIPW 1.75
1.75
1.75
2
ns
6
Read DQS Preamble Time
tRPRE 0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1 CK
Read DQS Postamble Time
tRPST 0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6 CK
Write DQS Preamble Setup Time tWPRES 0
0
0
0
CK
Write DQS Preamble Hold Time tWPREH 0.25
0.25
0.25
0.25
CK
Write DQS Postamble Time
tWPST 0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6 CK
Mode Register Set Delay
tMRD
2
2
2
2
CK
Exit self refresh to Any Executable _tXSC
200
200
200
Command
200
CK 8
Average Periodic Refresh Interval tREFI
7.8
7.8
7.8
7.8 us
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps
ps
0.5
0
0
0.4
+50
0
0.3
+100
0
5. CK, /CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester correlation
7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
Rev. 0.1 / June 2004
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