HYMD532646B6-H Datasheet, PDF (14/30 Pages) Hynix Semiconductor – 1184pin Unbufferd DDR SDRAM DIMMs

1184pin Unbufferd DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
1GB, 128M x 72 ECC Unbuffered DIMM: HYMD512726B[P]8[J]
Symbol
Test Condition
Speed
Unit
DDR400B DDR333 DDR266B
One bank; Active - Precharge; tRC=tRC(min);
IDD0
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
1800
1665
1440
mA
changing once per clock cycle
One bank; Active - Read - Precharge; Burst
IDD1 Length=2; tRC=tRC(min); tCK=tCK(min); address
2250
2025
1710
mA
and control inputs changing once per clock cycle
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
180
180
180
mA
/CS=High, All banks idle; tCK=tCK(min); CKE=
IDD2F High; address and control inputs changing once
630
630
630
mA
per clock cycle. VIN=VREF for DQ, DQS and DM
IDD3P
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
216
216
216
mA
/CS=HIGH; CKE=HIGH; One bank; Active-Pre-
charge; tRC=tRAS(max); tCK=tCK(min); DQ, DM
IDD3N and DQS inputs changing twice per clock cycle;
900
810
720
mA
Address and other control inputs changing once
per clock cycle
Burst=2; Reads; Continuous burst; One bank
IDD4R active; Address and control inputs changing once
2970
2655
2250
mA
per clock cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank
IDD4W
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
2970
2655
2250
mA
inputs changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
IDD5 10*tCK for DDR266A & DDR266B at 133Mhz; dis-
3150
2925
2700
mA
tributed refresh
IDD6
CKE=<0.2V; External clock on;
tCK =tCK(min)
Normal
Low Power
90
45
90
45
90
mA
45
mA
IDD7
Four bank interleaving with BL=4 Refer to the fol-
lowing page for detailed test condition
5310
4545
3780
mA
Note
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 / May. 2005
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