HYMD532646B6-H Datasheet, PDF (11/30 Pages) Hynix Semiconductor – 1184pin Unbufferd DDR SDRAM DIMMs

1184pin Unbufferd DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
512MB, 64M x 64 Unbuffered DIMM: HYMD564646B[P]8[J]
Symbol
Test Condition
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min); CKE=
High; address and control inputs changing once
per clock cycle. VIN=VREF for DQ, DQS and DM
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Pre-
charge; tRC=tRAS(max); tCK=tCK(min); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once
per clock cycle
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; dis-
tributed refresh
CKE=<0.2V; External clock on;
tCK =tCK(min)
Normal
Low Power
Four bank interleaving with BL=4 Refer to the fol-
lowing page for detailed test condition
DDR400B
1200
1600
80
280
96
400
2240
2240
2400
40
20
4320
Speed
DDR333
1120
1440
80
280
96
360
2000
2000
2240
40
20
3680
DDR266B
Unit
Note
960
mA
1200
mA
80
mA
280
mA
96
mA
320
mA
1680
mA
1680
mA
2080
mA
40
mA
20
mA
3040
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 / May. 2005
11