HYMD532646B6-H Datasheet, PDF (12/30 Pages) Hynix Semiconductor – 1184pin Unbufferd DDR SDRAM DIMMs

1184pin Unbufferd DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
512MB, 64M x 72 ECC Unbuffered DIMM: HYMD564726B[P]8[J]
Symbol
Test Condition
DDR400B
Speed
DDR333
DDR266B
Unit
Note
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min); CKE=
High; address and control inputs changing once
per clock cycle. VIN=VREF for DQ, DQS and DM
One bank active ; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Pre-
charge; tRC=tRAS(max); tCK=tCK(min); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once
per clock cycle
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; dis-
tributed refresh
1350
1800
90
315
108
450
2520
2520
2700
1260
1620
90
315
108
105
2250
2250
2520
1080
mA
1350
mA
90
mA
315
mA
108
mA
360
mA
1890
mA
1890
mA
2340
mA
IDD6
CKE=<0.2V; External clock on;
tCK =tCK(min)
Normal
Low Power
45
23
45
23
45
mA
23
mA
IDD7
Four bank interleaving with BL=4 Refer to the fol-
lowing page for detailed test condition
4860
4140
3420
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 / May. 2005
12