HYMD216646D6-K Datasheet, PDF (12/30 Pages) Hynix Semiconductor – 1184pin Unbuffered DDR SDRAM DIMMs

1184pin Unbuffered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
256MB, 32M x 72 ECC Unbuffered DIMM: HYMD232726D[P]8[J]
Symbol
Test Condition
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
One bank; Active - Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
One bank; Active - Read - Precharge; Burst
Length=2; tRC=tRC(min); tCK=tCK(min); address
and control inputs changing once per clock cycle
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=High, All banks idle; tCK=tCK(min); CKE=
High; address and control inputs changing once
per clock cycle. VIN=VREF for DQ, DQS and DM
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
/CS=HIGH; CKE=HIGH; One bank; Active-Pre-
charge; tRC=tRAS(max); tCK=tCK(min); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once
per clock cycle
Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
inputs changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; dis-
tributed refresh
CKE=<0.2V; External clock on; tCK Normal
=tCK(min)
Low Power
IDD7
Four bank interleaving with BL=4 Refer to the fol-
lowing page for detailed test condition
DDR400
810
900
90
540
135
450
1620
1620
1350
27
14
2070
Speed
Unit Note
DDR333 DDR266A DDR266B
720
630
630
mA
900
810
810
mA
90
90
90
mA
450
360
360
mA
135
135
135
mA
405
360
360
mA
1440
1350
1350
mA
1440
1350
1350
mA
1350
27
14
1980
1260
27
14
1800
1260
mA
27
mA
14
mA
1800
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.2 / May. 2005
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