HYMD216646D6-K Datasheet, PDF (10/30 Pages) Hynix Semiconductor – 1184pin Unbuffered DDR SDRAM DIMMs

1184pin Unbuffered DDR SDRAM DIMMs
IDD SPECIFICATION AND CONDITIONS (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
128MB, 16M x 64 Unbuffered DIMM: HYMD232646D[P]6[J]
Symbol
Test Condition
Speed
Unit
DDR400 DDR333 DDR266A DDR266B
One bank; Active - Precharge; tRC=tRC(min);
IDD0
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
360
320
280
280
mA
changing once per clock cycle
One bank; Active - Read - Precharge; Burst
IDD1 Length=2; tRC=tRC(min); tCK=tCK(min); address
400
400
360
360
mA
and control inputs changing once per clock cycle
IDD2P
All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)
40
40
40
40
mA
/CS=High, All banks idle; tCK=tCK(min); CKE=
IDD2F High; address and control inputs changing once
240
200
160
160
mA
per clock cycle. VIN=VREF for DQ, DQS and DM
IDD3P
One bank active; Power down mode; CKE=Low,
tCK=tCK(min)
60
60
60
60
mA
/CS=HIGH; CKE=HIGH; One bank; Active-Pre-
charge; tRC=tRAS(max); tCK=tCK(min); DQ, DM
IDD3N and DQS inputs changing twice per clock cycle;
200
180
160
160
mA
Address and other control inputs changing once
per clock cycle
Burst=2; Reads; Continuous burst; One bank
IDD4R active; Address and control inputs changing once
800
760
680
680
mA
per clock cycle; tCK=tCK(min); IOUT=0mA
Burst=2; Writes; Continuous burst; One bank
IDD4W
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM and DQS
800
760
680
680
mA
inputs changing twice per clock cycle
tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
IDD5 10*tCK for DDR266A & DDR266B at 133Mhz; dis-
600
600
560
560
mA
tributed refresh
CKE=<0.2V; External clock on; tCK Normal
12
12
12
12
mA
IDD6 =tCK(min)
Low Power
6
6
6
6
mA
IDD7
Four bank interleaving with BL=4 Refer to the fol-
lowing page for detailed test condition
1000
960
880
880
mA
Note
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.2 / May. 2005
10