HY57V161610D-I Datasheet, PDF (1/11 Pages) Hynix Semiconductor – 2 Banks x 512K x 16 Bit Synchronous DRAM

HY57V161610D-I
2 Banks x 512K x 16 Bit Synchronous DRAM
DESCRIPTION
THE Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the Mobile applications
which require low power consumption and industrial temperature range. HY57V161610D is organized as 2banks of
524,288x16.
HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-
width. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline
design is not restricted by a `2N` rule.)
FEATURES
• Single 3.0V to 3.6V power supply^Note1)
• Auto refresh and self refresh
• All device pins are compatible with LVTTL interface • 4096 refresh cycles / 64ms
• JEDEC standard 400mil 50pin TSOP-II with 0.8mm • Programmable Burst Length and Burst Type
of pin pitch
- 1, 2, 4, 8 and Full Page for Sequence Burst
• All inputs and outputs referenced to positive edge of
system clock
- 1, 2, 4 and 8 for Interleave Burst
• Data mask function by UDQM/LDQM
• Programmable CAS Latency ; 1, 2, 3 Clocks
• Internal two banks operation
ORDERING INFORMATION
Part No.
HY57V161610DTC-55I
HY57V161610DTC-6I
HY57V161610DTC-7I
HY57V161610DTC-10I
Clock Frequency
183MHz
166MHz
143MHz
100MHz
Organization
Interface
2Banks x 512Kbits x 16
LVTTL
Package
400mil
50pin TSOP II
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied
Rev. 0.3/Mar. 02
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