HDMP-1022 Datasheet, PDF (9/40 Pages) Agilent(Hewlett-Packard) – Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os

HDMP-1022 (Tx) Timing
Figure 6 shows the Tx timing
diagram. Under normal
operations, the Tx PLL locks an
internally generated clock to the
incoming STRBIN. The incoming
data, D0-D19, ED, FF, DAV*,
CAV*, and FLAG, are latched by
this internal clock. For
MDFSEL=0, the input rate of
STRBIN is expected to be the
same as the parallel data rate. For
MDFSEL=1, STRBIN should be
1/2 of the incoming parallel data
rate. The data must be valid
before it’s sampled for a set-up
time (t_s), and remain valid after
it’s sampled for a hold time (t_h).
In single frame mode
(MDFSEL=0), t_s and t_h are
referenced to the rising edge of
STRBIN. In double frame mode
(MDFSEL=1), t_s and t_h are
referenced to half the frame
period from the rising or falling
edge of STRBIN plus 4 ns.
STRBOUT appears after this
reference with a delay of ∆T_strb.
The rate of STRBOUT is always
the same as the word rate of the
incoming data, independent of
MDFSEL.
The start of a frame, D0, in the
high speed serial output occurs
after a delay of t_d after the rising
edge of the STRBIN. The typical
value of t_d may be calculated by
using the following formula.
HDMP-1022 (Tx) Timing Characteristics
Tc = 0°C to +85°C, V_CC = 4.5 V to 5.5 V
Symbol
t_s
Parameter
Setup Time, for D₀-D₁₉ Relative to Rising Edge of STRBIN,
ED, FF, DAV*, CAV* and FLAG
t_h
∆T_strb
Hold Time, for D₀-D₁₉ Relative to Rising Edge of STRBIN,
ED, FF, DAV*, CAV* and FLAG
STRBOUT - STRBIN Delay at 64 MHz in 20-bit Mode
Units Min. Typ. Max.
nsec 2.0*
nsec 2.0*
nsec
4.0
*In double frame mode, due to the internal clock delay, t_s and t_h are referenced to half the frame period plus 4 ns from the rising or
falling edge of STRBIN.
STRBIN
MDFSEL = 0
STRBIN
MDFSEL = 1
1/2 FRAME PERIOD
D00 - D19
ED, FF
DAV*, CAV*
FLAG
STRBOUT
DOUT
HCLK
t_s
t_strb
t_d
Figure 6. HDMP-1022 (Tx) Timing Diagram.
624
t_h
D-FIELD
C-FIELD