HDMP-1022 Datasheet, PDF (21/40 Pages) Agilent(Hewlett-Packard) – Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os

Rx I/O Definition (cont’d.)
Name
SMRST0*
SMRST1*
STAT0
STAT1
STRBOUT
TCLK
TCLKSEL
V_CC
V_{CC_HS}
V_CCTTL
GND
GND_TTL
Pin Type
Signal
28 I-TTL State Machine Reset Inputs: Each of these active-low input pins
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reset the Rx state machine to the initial start-up state. This initiates
a complete PLL restart and handshake at both ends of the duplex
link. Normally, SMCRST0* is connected to a power-up reset circuit
or a host system reset signal. The SMCRST1* input is normally
connected to the Tx LOCKED output. The LOCKED signal holds the
state-machine in the start-up state until the Tx PLL is locked.
27 O-TTL State Machine Status Outputs: These outputs indicate the current
26
state-machine state. They are used to directly control the Tx ED,
Tx FF, Rx FDIS, and Rx ACTIVE lines.
35 O-TTL Recovered Frame-rate Data Clock Output: This output is the PLL
recovered frame rate clock. D0-D19, FLAG, DAV, CAV, FF, LINKRDY,
and ERROR should all be latched on the rising edge of STRBOUT.
12 I-TTL External VCO Replacement Test Clock: When TCLKSEL in
enabled, this input is used in place of the normal VCO signal,
effectively disabling the PLL and allowing the user to provide an
external retiming clock for testing.
10 I-ECL Enable Test Clock Input: When this input is active, the TCLK,
TCLK* inputs are used in place of the normal VCO signal. This
feature is useful both for synchronous systems and for chip testing.
5
S Ground: Normally 5.0 volts. This power supply is used for all the
23
core logic other than the output drivers.
24
33
44
63
64
73
78
13
S High Speed Supply: Normally 5.0 volts. This ground is used to provide
clean references for the high speed DIN, DIN*, LIN, LIN* inputs.
32
S TTL Power Supply: Normally 5.0 volts. Used for all TTL receiver
52
output buffer cells.
53
72
21
S Power: Normally 0 volts. Tie to ground.
22
42
62
79
80
31
S TTL Power: Normally 0 volts. Tie to ground.
41
61
74
636