HDMP-1022 Datasheet, PDF (10/40 Pages) Agilent(Hewlett-Packard) – Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os

HDMP-1024 (Rx) Timing
Figure 7 is the Rx timing diagram
when the internal PLL is locked to
the incoming serial data. The size
of the input data frame can be
either 20 bits or 24 bits,
depending on the setting of
M20SEL. Independent of the
frame size, STBROUT’s falling
edge is aligned to the data frame’s
boundary, while the rising edge is
in the center of the data frame.
The synchronous outputs,
D0-D19, LINKRDY*, DAV*, CAV*,
FF, ERROR, and FLAG, are
updated for every data frame,
with a delay of t_d1 after the falling
edge of STRBOUT. There is a
latency delay of two frames from
the input of the serial data frame
to the update of the synchronous
outputs.
The state machine outputs,
STAT0, and STAT1, appear with
the falling edge of STRBOUT after
a delay of t_d2. Referring to Figure
15, if the RESET or ERROR signal
is present, Rx will go into State 0.
After 128 frames, it will go into
State 1. Transitions after that
depend on the training sequence.
HDMP-1024 (Rx) Timing Characteristics
Tc = 0°C to +85°C, V_CC = 4.5 V to 5.5 V
Symbol
Parameter
t-valid before Synchronous Output Setup Time at 75 MHz in 16-bit Mode
t-valid after Synchronous Output Hold Time at 75 MHz in 16-bit Mode
t_d1
Synchronous Output Delay Referenced to the Falling Edge
of STRBOUT. Delay is Measured with Reference to 1.5 V
Logic Threshold
t_d2
State Machine Output Delay Referenced to the Falling
Edge of STRBOUT
Units
nsec
nsec
nsec
nsec
Min.
3.0
3.0
Typ.
Max.
2.0
4.0
Note: Typical Rx STRBOUT duty cycle range is 45% to 65%.
DIN
D-FIELD
C-FIELD
CLK
t-VALID BEFORE
STRBOUT
D00 - D19
LINKRDY*
DAV*, CAV*
FF, ERROR
FLAG
STAT1
STAT0
t_d1
t_d2
Figure 7. HDMP-1024 (Rx) Timing Diagram.
t-VALID AFTER
625