HDMP-1022 Datasheet, PDF (25/40 Pages) Agilent(Hewlett-Packard) – Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os

HDMP-1022 (Tx), HDMP-1024 (Rx)
Control Frame Structure
M20SEL Not Asserted (16 bit mode)
D0 - D6
D₀ - D₆
D₀ - D₆
D-Field
D7 D8 D9 - D15 C0
0
1
D₇ - D₁₃
0
1
0
D₇ - D₁₃
1
C-Field
C1 C2 C3
0
11
1
00
HDMP-1022 (Tx), HDMP-1024 (Rx)
Control Frame Structure
M20SEL Asserted (20 bit mode)
D0 - D8
D₀ - D₈
D₀ - D₈
D-Field
D9 D10 D11-D19 C0
0
1
D₉-D₁₇
0
1
0
D₉-D₁₇
1
C-Field
C1 C2 C3
0
11
1
00
Fill Frame Codes
Two logical fill frames are
provided: FF0 and FF1. FF0 is
physically a 50% duty cycle wave
form with its sole rising edge
occurring between C1 and C2.
Logical FF1 toggles between two
different physical codes, the first
of which advances the falling edge
of FF0 by one bit, the second of
which retards the falling edge of
FF0 by one bit. Two logical fill
frame types are required for link
start up in duplex mode.
HDMP-1022 (Tx), HDMP-1024 (Rx)
Fill Frame Structure
M20SEL Not Asserted (16 bit mode)
Fill Frame
0
1a
1b
1111111
1111111
1111111
D-Field
10
11
00
0000000
0000000
0000000
C-Field
0011
0011
0011
HDMP-1022 (Tx), HDMP-1024 (Rx)
Fill Frame Structure
M20SEL Asserted (20 bit mode)
Fill Frame
0
1a
1b
111111111
111111111
111111111
D-Field
10
11
00
000000000
000000000
000000000
C-Field
0011
0011
0011
640