HDMP-0422 Datasheet, PDF (9/14 Pages) Agilent(Hewlett-Packard) – Single Port Bypass Circuit with CDR & Data Valid Detection Capability for Fibre Channel Arbitrated Loops

Guaranteed Operating Rates
VCC = 3.15 V to 3.45 V.
FC Serial Clock Rate (MBd)
Min.
Max.
1,040
1,080
GE Serial Clock Rate (MBd)
Min.
Max.
1,240
1,260
CDR Reference Clock Requirements
V_CC = 3.15 V to 3.45 V.
Symbol Parameter
f
Nominal Frequency (Fibre Channel)
f
Nominal Frequency (Gigabit Ethernet)
Ftol
Frequency Tolerance
Symm Symmetry (Duty Cycle)
Units
MHz
MHz
ppm
%
Min.
–100
40
Typ. Max.
106.25
125
+100
60
Locking Characteristics
V_CC = 3.15 V to 3.45 V.
Parameter
Bit Sync Time (phase lock)
Frequency Lock at Powerup
Units
bits
µs
Max.
2500
500
Output Jitter Characteristics
VCC = 3.15 V to 3.45 V.
Symbol Parameter
RJ^[1] Random Jitter at TO_NODE pins (1 sigma rms)
DJ^[1] Deterministic Jitter at TO_NODE pins (pk-pk)
Units Typ.
ps 5
ps 20
Note:
1. Please refer to Figures 7 and 8 for jitter measurement setup information.
Max.
Figure 6. Eye diagram of TO_NODE[1]± high speed differential output (50 Ω termination).
Note: Measurement taken with a 2⁷-1 PRBS input to FM_NODE[0]±
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