HDMP-0422 Datasheet, PDF (8/14 Pages) Agilent(Hewlett-Packard) – Single Port Bypass Circuit with CDR & Data Valid Detection Capability for Fibre Channel Arbitrated Loops

Absolute Maximum Ratings
TA = 25ºC, except as specified. Operation in excess of any of these conditions may result in permanent damage to this
device. Continuous operation at these minimum or maximum ratings is not recommended.
Symbol
Parameter
Units
Min.
Max.
V_CC
VIN,LVTTL
Supply Voltage
LVTTL Input Voltage
V
–0.5
4.0
V
–0.5
VCC + 0.5^[1]
V_{IN,HS_IN}
HS_IN Input Voltage (Differential)
mV
200
2000
I_O,LVTTL
LVTTL Output Sink/Source Current
mA
±13
Tstg
Storage Temperature
°C
–65
+150
T_j
Junction Temperature
°C
0
+125
Note:
1. Must remain less than or equal to absolute maximum VCC voltage of 4.0 V.
DC Electrical Specifications
VCC = 3.15 V to 3.45 V.
Symbol
Parameter
V_IH,LVTTL
LVTTL Input High Voltage Range
VIL,LVTTL
LVTTL Input Low Voltage Range
V_OH,LVTTL
LVTTL Output High Voltage Range, I _OH = -400 µA
V_OL,LVTTL
LVTTL Output Low Voltage Level, I _OL = 1 mA
IIH,LVTTL
Input High Current (Magnitude), V IN = 2.4 V, VCC = 3.45 V
I_IL,LVTTL
Input Low Current (Magnitude), V_IN = 0.4 V, V_CC = 3.45 V
I_CC
Total Supply Current, T_A = 25°C
Units
V
V
V
V
µA
µA
mA
Min. Typ. Max.
2.0
0.8
2.2
V_CC
0
0.6
40
–600
140
AC Electrical Specifications
V_CC = 3.15 V to 3.45 V.
Symbol
Parameter
Units Min. Typ. Max.
TLOOP_LAT Total Loop Latency from FM_NODE[0] to TO_NODE[0]
ns
3.0
T_{CELL_LAT}
Per Cell Latency from FM_NODE[1] to TO_NODE[0]
ns
2.0
t_r,LVTTLin
Input LVTTL Rise Time Requirement, 0.8 V to 2.0 V
ns
2.0
tf,LVTTLin
Input LVTTL Fall Time Requirement, 2.0 V to 0.8 V
ns
2.0
t_r,LVTTLout
Output TTL Rise Time, 0.8 V to 2.0 V, 10 pF Load
ns
1.7 3.3
t_f,LVTTLout
Output TLL Fall Time, 2.0 V to 0.8 V, 10 pF Load
ns
1.7 2.4
trs,HS_OUT
HS_OUT Single-Ended Rise Time, 20% to 80%
ps
200 300
t_{fs,HS_OUT}
HS_OUT Single-Ended Fall Time, 20% to 80%
ps
200 300
t_{rd,HS_OUT}
HS_OUT Differential Rise Time, 20% to 80%
ps
200 300
tfd,HS_OUT
HS_OUT Differential Fall Time, 20% to 80%
ps
200 300
V_{IP,HS_IN}
HS_IN Required Pk-Pk Differential Input Voltage
mV
200 1200 2000
V_{OP,HS_OUT} HS_OUT Pk-Pk Differential Output Voltage (Z0 = 75 Ω, Figure 10) mV
1100 1400 2000
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