HCPL9000 Datasheet, PDF (9/12 Pages) Agilent(Hewlett-Packard) – High Speed Digital Isolators

Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at T_A=+25°C, V_DD1 = V_DD2 = +5.0 V.
Parameter
Symbol
Min.
Typ.
Max.
Units Test Conditions
Quiescent Supply Current 1
I_DD1
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
0.012
0.012
2.5
0.024
5.0
2.5
0.018
0.018
3.0
0.036
6.0
3.0
mA
V_IN = 0V
Quiescent Supply Current 2
I_DD2
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
mA
V_IN = 0V
5.0
6.0
5.0
6.0
2.5
3.0
8.0
12.0
5.0
6.0
6.0
9.0
Logic Input Current
Logic High Output Voltage
Logic Low Output Voltage
I_IN
-10
10
µA
V_OH
V_DD2 – 0.1
V_DD2
V
I_OUT= -20 µA, V_IN= V_IH
0.8*V_DD2
V_DD2 – 0.5
V
I_OUT= -4 mA, V_IN= V_IH
V_OL
0
0.1
V
I_OUT= 20 µA, V_IN= V_IL
0.5
0.8
V
I_OUT= 4 mA, V_IN= V_IL
Switching Specifications
Maximum Data Rate
Clock Frequency
100
110
MBd _{CL = 15 pF}
fmax
50
MHz
Propagation Delay Time to Logic
t_PHL
Low Output
10
15
ns
Propagation Delay Time to Logic
t_PLH
High Output
10
15
ns
Pulse Width
t_PW
10
Pulse Width Distortion^[1]
|PWD|
2
|t_PHL – t_PLH|
Propagation Delay Skew^[2]
t_PSK
4
Output Rise Time (10 – 90%)
t_R
1
Output Fall Time (10 – 90%)
t_F
1
Propagation Delay Enable to Output (Single Channel)
High to High Impedance
t_PHZ
3
Low to High Impedance
t_PLZ
3
High Impedance to High
t_PZH
3
High Impedance to Low
t_PZL
3
Channel-to-Channel Skew
t_CSK
2
(Dual and Quad Channels)
ns
3
ns
6
ns
3
ns
3
ns
5
ns
5
ns
5
ns
5
ns
3
ns
Common Mode Transient Immunity
|CM_H|
15
18
(Output Logic High or Logic Low)^[3]
|CM_L|
kV/µs V_cm = 1000V
Notes:
1. PWD is defined as |t_PHL -t_PLH|. %PWD is equal to the PWD divided by the pulse width.
2. t_PSK is equal to the magnitude of the worst case difference in t_PHL and/or t_PLH that will be seen between units at 25°C.
3. CM_H is the maximum common mode voltage slew rate that can be sustained while maintaining V_OUT > 0.8V_DD2. CM_L is the maximum common mode
input voltage that can be sustained while maintaining V_OUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Agilent recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
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