HCPL9000 Datasheet, PDF(10/12 Page) Agilent(Hewlett-Packard)

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HCPL9000 Datasheet, PDF (10/12 Pages) Agilent(Hewlett-Packard) – High Speed Digital Isolators

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Applications Information

Power Consumption

The HCPL-90xx and HCPL-09xx

CMOS digital isolators achieves

low power consumption from the

manner by which they transmit

data across isolation barrier. By

detecting the edge transitions of

the input logic signal and con-

verting this to a narrow current

pulse, which drives the isolation

barrier, the isolator then latches

the input logic state in the output

latch. Since the current pulses

are narrow, about 2.5 ns wide, the

power consumption is indepen-

dent of mark-to-space ratio and

solely dependent on frequency.

The approximate power supply

current per channel is:

I(Input) = 40(f/fmax)(1/4) mA

where f = operating frequency,

fmax = 50 MHz.

Signal Status on Start-up and

Shut Down

To minimize power dissipation,

the input signals to the channels

of HCPL-90xx and HCPL-09xx

digital isolators are differenti-

ated and then latched on the

output side of the isolation

barrier to reconstruct the signal.

This could result in an ambigu-

ous output state depending on

power up, shutdown and power

loss sequencing. Therefore, the

designer should consider the

inclusion of an initialization

signal in this start-up circuit.

Bypassing and PC Board Layout

The HCPL-90xx and HCPL-09xx

digital isolators are extremely

easy to use. No external interface

circuitry is required because the

isolators use high-speed CMOS IC

technology allowing CMOS logic

to be connected directly to the

inputs and outputs. As shown in

Figure 1, the only external

components required for proper

operation are two 47 nF ceramic

capacitors for decoupling the

power supplies. For each capaci-

tor, the total lead length between

both ends of the capacitor and the

power-supply pins should not

exceed 20 mm. Figure 2 illustrates

the recommended printed circuit

board layout for the HCPL-9000

or HCPL-0900. For data rates in

excess of 10MBd, use of ground

planes for both GND1 and GND2 is

highly recommended.

VDD1

IN1

NC 3

GND1

7 VOE

GND2

VDD2

OUT1

Note: C1, C2 = 47 nF ceramic capacitors

Figure 1. Functional Diagram of Single Channel HCPL-0900 or HCPL-0900.

VDD1

IN1

GND1

Figure 2. Recommended Printed Circuit Board Layout.

VOE

VDD2

OUT1

GND2

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