HCPL9000 Datasheet, PDF (12/12 Pages) Agilent(Hewlett-Packard) – High Speed Digital Isolators

Propagation delay skew repre-
sents the uncertainty of where
an edge might be after being sent
through a digital isolator. Figure
5 shows that there will be uncer-
tainty in both the data and clock
lines. It is important that these
two areas of uncertainty not
overlap, otherwise the clock
signal might arrive before all of
the data outputs have settled, or
some of the data outputs may
start to change before the clock
signal has arrived. From these
considerations, the absolute
minimum pulse width that can be
sent through digital isolators in a
parallel application is twice t_PSK.
A cautious design should use a
slightly longer pulse width to
ensure that any additional
uncertainty in the rest of the
circuit does not cause a problem.
Figure 6 shows the minimum
pulse width, rise and fall time,
and propagation delay enable to
output waveforms for HCPL-9000
or HCPL-0900.
50%
V_IN
50%
V_OUT
90%
90%
t_PZL
t_PLZ
t_PHZ
t_PZH
10% 10%
t_PW
t_F
t_R
V_OE
t_PW
Minimum Pulse Width
t_PLZ
Propagation Delay, Low to High Impedance
t_PZH
Propagation Delay, High Impedance to High
t_PHZ
Propagation Delay, High to High Impedance
t_PZL
Propagation Delay, High Impedance to Low
t_R
Rise Time
t_F
Fall Time
Figure 6. Timing Diagrams to Illustrate the Minimum Pulse Width, Rise and Fall Time, and Propagation Delay Enable to
Output Waveforms for HCPL-9000 or HCPL-0900.
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Data subject to change.
Copyright © 2002 Agilent Technologies, Inc.
October 31, 2002
5988-5626EN