HDMP-1638 Datasheet, PDF (4/19 Pages) Agilent(Hewlett-Packard) – Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs

4
Frame Demux and
Byte Sync
The FRAME DEMUX AND BYTE
SYNC block is responsible for
restoring the 10-bit parallel
data from the high speed serial
bit stream. This block is also
responsible for recognizing the
comma character (or a K28.5
character) of positive disparity
(0011111xxx). When recognized,
the FRAME DEMUX AND BYTE
SYNC block works with the RX
PLL/CLOCK RECOVERY block
to properly align the receive byte
clocks to the parallel data. When
a comma character is detected
and realignment of the receiver
byte clocks (RBC1/RBC0) is
necessary, these clocks are
stretched, not slivered, to the
next possible correct alignment
position. These clocks will be fully
aligned by the start of the second
2-byte ordered set. The second
comma character received shall
be aligned with the rising edge of
RBC1. As per the 8B/10B encoding
scheme, comma characters must
not be transmitted in consecutive
bytes to allow the receiver byte
clocks to maintain their proper
recovered frequencies.
Output Drivers
The OUTPUT DRIVERS present
the 10-bit parallel recovered data
byte properly aligned to the receive
byte clocks (RBC1/RBC0),
as shown in Figure 5. These
output data buffers provide
TTL compatible signals.
Signal Detect
The SIGNAL DETECT block
examines the differential
amplitude of the inputs ± DINB.
When this input signal is too
small, it outputs a logic 0 at
SIG_DET (refer to SIG_DET pin
definition for detection thresholds).
When the signal at ± DINB is
of a valid amplitude, SIG_DET
is set to logic 1.
HDMP-1638 (Transmitter Section)
Timing Characteristics
T_A = 0 °C to +70 °C, V_CC = 3.15 V to 3.45 V
Symbol
Parameter
Units Min. Typ.
Max.
t_setup Setup Time
nsec 1.5
t_hold
Hold Time
nsec 1.0
t_txlat^[1] Transmitter Latency nsec
3.5
bits
4.4
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the
latching in of the parallel data word (as triggered by the rising edge of the transmit
byte clock, REFCLK) and the transmission of the first serial bit of that parallel word
at either output pair (defined by the rising edge of the first bit transmitted).