HDMP-1638 Datasheet, PDF (15/19 Pages) Agilent(Hewlett-Packard) – Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs

15
NAME
PIN
GND_TXHS
1
GND_TXTTL
14
N/C
27,12
LOOPEN
19
RBC1
30
RBC0
31
+REFCLK
22
-REFCLK
23
RX[0]
45
RX[1]
44
RX[2]
43
RX[3]
41
RX[4]
40
RX[5]
39
RX[6]
38
RX[7]
36
RX[8]
35
RX[9]
34
RXCAP0
48
RXCAP1
49
TYPE
S
S
I-TTL
O-TTL
PECL
O-TTL
SIGNAL
Ground: Normally 0 volts.
TTL Transmitter Ground: Normally 0 volts. Used for the
TTL input cells of the transmitter section.
These pins are connected to an isolated pad and have no
functionality. They may be left open, however, TTL levels
may also be applied to these pins.
Loopback Enable Input: When set high, the high speed
serial signal is internally wrapped from the transmitter’s
serial loopback outputs back to the receiver’s loopback
inputs. Also when in loopback mode, the ± DOUT outputs
are held static at logic 1. When set low, ± DOUT outputs
and ± DIN inputs are active.
Receiver Byte Clocks: The receiver section recovers
two 62.5 MHz receive byte clocks. These two clocks are
180 degrees out of phase. The receiver parallel data out-
puts are alternately clocked on the rising edge of these
clocks. The rising edge of RBC1 aligns with the output of
the comma character (for byte alignment) when detected.
Reference Clock and Transmit Byte Clock: A 125
MHz clock supplied by the host system. The transmitter
section accepts this signal as the frequency reference
clock. It is multiplied by 10 to generate the serial bit
clock and other internal clocks. The transmit side also
uses this clock as the transmit byte clock for the
incoming parallel data TX[0]..TX[9]. It also serves as the
reference clock for the receive portion of the transceiver.
Data Outputs: One 10 bit data byte. RX[0] is the first
bit received. RX[0] is the least significant bit. When there
is a loss of input signal at ± DINB and RXSEL is high,
these outputs are held static at logic 1. Refer to SIG_DET
(pin 26) pin definition for more details.
C
Loop Filter Capacitor: A loop filter capacitor for the
internal PLL must be connected across the RXCAP0 and
RXCAP1 pins. (typical value = 0.1 µF)