HDMP-1638 Datasheet, PDF (2/19 Pages) Agilent(Hewlett-Packard) – Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs

2
The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two
62.5 MHz receiver byte clocks
which are 180 degrees out of
phase with each other. The
parallel data is properly aligned
with the rising edge of alternating
clocks.
For test purposes, the transceiver
provides for on-chip local loop-
back functionality controlled
through an external input pin.
Additionally, the byte synchro-
nization feature may be disabled.
This may be useful in proprietary
applications which use alternative
methods to align the parallel data.
PROTOCOL DEVICE
BYTSYNC
HDMP-1638
TRANSMITTER SECTION
PLL
PLL
RECEIVER SECTION
REFCLK
ENBYTSYNC
RXSEL
Figure 1. Typical Application Using the HDMP-1638.
SERIAL DATA OUT
SERIAL DATA IN
HDMP-1638 Block
Diagram
The HDMP-1638 was designed
to transmit and receive 10-bit
wide parallel data over high-
speed serial lines. The parallel
data applied to the transmitter is
expected to be encoded per the
Gigabit Ethernet specification,
which uses an 8B/10B encoding
scheme with special reserve
characters for link management
purposes. In order to accomplish
this task, the HDMP-1638
incorporates the following:
• TTL Parallel I/O’s
• High Speed Phase Locked Loops
• Parallel to Serial Converter
• Serial Clock and Data Recovery
• Comma Character Recognition
• Byte Alignment Circuitry
• Serial to Parallel Converter
DATA BYTE
TX[0-9]
TXCAP0
TXCAP1
± REFCLK
RXCAP0
RXCAP1
RBC0
RBC1
DATA BYTE
RX[0-9]
FRAME
MUX
TX
PLL/CLOCK
GENERATOR
INTERNAL
TX CLOCKS
OUTPUT
SELECT
INTERNAL
LOOPBACK
INPUT
SELECT
RX
PLL/CLOCK
RECOVERY
FRAME
DEMUX
AND
BYTE SYNC
INTERNAL
RX CLOCKS
INPUT
SAMPLER
BYTSYNC ENBYTSYNC
RXSEL
Figure 2. HDMP-1638 Transceiver Block Diagram.
± DOUTA
± DOUTB
LOOPEN
± DINA
± DINB