HDMP-1638 Datasheet, PDF (17/19 Pages) Agilent(Hewlett-Packard) – Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs

17
V_CC
V_CC*
GND_TXHS
C_PLLR
RXCAP0
GND_RXTTL
GND_TXTTL
GND_TXA
TXCAP1
V_CC_RXTTL
V_CC
HDMP-1638
TOP VIEW
V_CC_RXTTL
GND_RXTTL
C_PLLT
V_CC
V_CC*
* SUPPLY VOLTAGE INTO V_CC_RXA AND V_CC_TXA SHOULD BE FROM A LOW NOISE
SOURCE. ALL BYPASS CAPACITORS AND PLL FILTER CAPACITORS ARE 0.1 µF.
Figure 12: Power Supply Bypass.
Transceiver Power
Supply Bypass and Loop
Filter Capacitors
If desired, bypass capacitors may
be used on the power supply pins
of the HDMP-1638. All bypass
chip capacitors are 0.1 µF. The
V_CC_RXA and V_CC_TXA pins are
the analog power supply pins for
the PLL sections. The supply into
these pins should be clean with
minimum noise. Use of capacitors
as shown in Figure 12 is
mandatory for these pins. The
PLL loop filter capacitors and
their pin locations are also shown
on Figure 12. Notice that only
two capacitors are required;
C_PLLT for the transmitter and
C_PLLR for the receiver. Nominal
capacitance is 0.1 µF. The
maximum voltage across
the capacitors is on the order of
1 volt, so the capacitor can be a
low voltage type and physically
small. The PLL capacitors are
to be placed physically close
to the appropriate pins on the
HDMP-1638. Keeping the lines
short will prevent them from
picking up any stray noise from
surrounding lines or components.
Start Up Procedure:
The transceiver startup procedure(s) and the following conditions:
V_CC = +3.3 V ± 5 % and REFCLK = 125 MHz ± 100 ppm.
After the above conditions have been met, apply valid data using a
balanced code such as 8B/10B. Frequency lock occurs within 500 µs.
After frequency lock, phase lock occurs within 2500 bit times.