HDMP-1638 Datasheet, PDF (1/19 Pages) Agilent(Hewlett-Packard) – Gigabit Ethernet Transceiver Chip with Dual Serial I/O and Differential PECL Clock Inputs

Gigabit Ethernet Transceiver Chip
with Dual Serial I/O and
Differential PECL Clock Inputs
Technical Data
HDMP-1638 Transceiver
Features
• IEEE 802.3z Gigabit Ethernet
compatible, Supports
1250 MBd Gigabit Ethernet
• Based on X3T11 “10-Bit
Specification”
• Low Power Consumption
• Transmitter and Receiver
Functions Incorporated
Onto a Single IC
• 10 mm, 64-Pin Plastic
Package
• 5 Volt Tolerant I/Os
• 10-Bit Wide Parallel TTL
Compatible I/Os
• Single +3.3 V Power Supply
• Differential PECL Clock
Inputs
• Dual Serial I/O With
Receive Select
• 2kV ESD Protection on
All Pins
Applications
• 1250 MBd Gigabit Ethernet
Interface
• High Speed Proprietary
Interface
• Backplane Serialization/Bus
Extender
Description
The HDMP-1638 transceiver is a
single silicon bipolar integrated
circuit packaged in a plastic QFP
package. It provides a low-cost,
low-power physical layer solution
for 1250 MBd Gigabit Ethernet
or proprietary link interfaces.
It provides complete Serialize/
Deserialize (“SerDes”) for copper
transmission, incorporating both
the Gigabit Ethernet transmit and
receive functions into a single
device.
This chip is used to build a high
speed interface (as shown in
Figure 1) while minimizing
board space, power and cost.
It is compatible with the IEEE
802.3z specification.
The transmitter section accepts
10-bit wide parallel TTL data
and serializes this data into two
high speed serial data streams.
The parallel data is expected to
be “8B/10B” encoded data, or
equivalent. This parallel data is
latched into the input register
of the transmitter section on
the rising edge of the 125 MHz
reference clock (used as the
transmit byte clock).
The transmitter section’s PLL locks
to this user supplied 125 MHz
byte clock. This clock is then
multiplied by 10, to generate the
1250 MHz serial signal clock used
to generate the high speed
outputs. The high speed outputs
are capable of interfacing directly
to copper cables for electrical
transmission or to a separate
fiber optic module for optical
transmission.
The receiver section allows
for the selection of one of two
serial electrical data streams
at 1250 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto
the incoming serial signal and
recovers the high speed serial
clock and data. The serial data
is converted back into 10-bit
parallel data, recognizing the
8B/10B comma character to
establish byte alignment.
CAUTION: As with all semiconductor IC’s, it is advised that normal static precautions be taken in handling
and assembly of this component to prevent damage and/or degradation which may be induced by
electrostatic discharge (ESD).