RFM22 Datasheet, PDF (76/150 Pages) –

RFM22
Table 31. Interrupt or Status 1 Bit Set/Clear Description
Status
Bit
Name
Set/Clear Conditions
7
ifferr
Set if there is a FIFO overflow or underflow. Cleared by applying FIFO reset.
Set when the number of bytes written to TX FIFO is greater than the Almost Full
6
itxffafull threshold.Automatically cleared at the start of transmission when the number of bytes
in the FIFO is less than or equal to the threshold.
Set when the number of bytes in the TX FIFO is less than or equal to the Almost
5
ixtffaem Empty threshold. Automatically cleared when the number of data bytes in the TX
FIFO is above the Almost Empty threshold.
Set when the number of bytes in the RX FIFO is greater than the Almost Full threshold.
4
irxffafull
Cleared when the number of bytes in the RX FIFO is below the Almost Full threshold.
3
iext
External interrupt source.
Set once a packet is successfully sent (no TX abort). Cleared upon leaving FIFO
2
ipksent
mode or at the start of a new transmission.
Set up the successful reception of a packet (no RX abort). Cleared upon receiving
1
ipkvalid
and acknowledging the Sync Word for the next packet.
Set if the CRC computed from the RX packet differs from the CRC in the TX packet.
0
icrerror
Cleared at the start of reception for the next packet.
Table 30. When are Individual Status Bits Set/Cleared if not Enabled as Interrupts?
Status
Bit
Name
Set/Clear Conditions
Set if there is a FIFO Overflow or Underflow. It is cleared only by applying FIFO reset
7
ifferr
to the specific FIFO that caused the condition.
Will be set when the number of bytes written to TX FIFO is greater than the Almost Full
6
itxffafull threshold set by SPI. It is automatically cleared when we start transmitting and the FIFO data is
read out and the number of bytes left in the FIFO is smaller or equal to the threshold).
Will be set when the number of bytes (not yet transmitted) in TX FIFO is smaller or equal than
the Almost Empty threshold set by SPI. It is automatically cleared when we write enough data
5
ixtffaem
to TX FIFO so that the number of data bytes not yet transmitted is above the Almost Empty
threshold.
Will be set when the number of bytes received (and not yet read-out) in RX FIFO is greater than
4
irxffafull the Almost Full threshold set by SPI. It is automatically cleared when we read enough data from
RX FIFO so that the number of data bytes not yet read is below the Almost Full threshold.
3
iext
External interrupt source
Will go high once a packet is sent all the way through (no TX abort). This status will be cleaned
2
ipksent
if 1) We leave FIFO mode or 2) In FIFO mode we start a new transmission.
Goes high once a packet is fully received (no RX abort). It is automatically cleaned
1
ipkvalid
once we receive and acknowledge the Sync Word for the next packet.
Goes High once the CRC computed during RX differs from the CRC sent in the
0
icrerror
packet by the TX. It is cleaned once we start receiving new data in the next packet.
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