HMC714LP5 Datasheet, PDF (37/40 Pages) Hittite Microwave Corporation – DUAL RMS POWER DETECTOR 0.1 - 3.9 GHz

v05.0309
HMC714LP5 / 714LP5E
DUAL RMS POWER DETECTOR
0.1 - 3.9 GHz
12
PAR – Envelope Power Normalized To Average Power (Continued)
full description on crest factor optimization.
iPAR Reference Outputs: IREFA & IREFB
HMC714LP5E also provides two reference voltage outputs, IREF_A (pin 26) and IREF_B (pin 15) for A & B channels,
which when used with the INS_A/INS_B outputs allows cancellation of temperature and supply related variations of the
INS_A/INS_B DC offsets. INS_A/INS_B DC offsets are equal to the IREF_A/IREF_B reference voltages, and these levels
corresponds to the envelope-to-average ratio (EAR) or peak-to-average ratio (PAR) of an unmodulated carrier (CW-
tone crest factor = 3 dB). For the best cancellation of the effects of temperature and supply voltage on INS_A/INS_B DC
offsets, load both the INS_A/INS_B and IREF_A/IREF_B outputs with an equivalent RC network.
Propagation Delay of INS_A & INS_B
The proper operation of the iPAR feature depends on
the proper settling of the RMS outputs because both
the iPAR feature and the RMS detection feature share
the same internal structures. After internal mechanisms
of the detector have settled, the RMS outputs (RMS_A &
RMS_B) provide a reading of input average power while
iPAR outputs (INS_A & INS_B) provides the instantaneous
(or peak) power value of the input signal. There is of
course some finite propagation delay from the instant of
input power change to the change of INS_A (INS_B). That
propagation delay is defined by the external capacitor,
Cext. The figure illustrates the propagation delay from a
900 MHz, 6-tone (multi-carrier) input signal at -10 dBm
average power to the INS_A output of HMC714LP5E. As
illustrated, the propagation delay is 26 nsec with the
detector configured with the wideband, single-ended
input interface. The use of the differential input interface
with the balun increases the propagation delay to 37 nsec
under similar test conditions.
Propagation Delay with Wideband
Single Ended Input Itnerface
0.2
2.85
0.15
2.49
0.1
2.14
26nS
0.05
1.78
0
1.42
-0.05
1.07
-0.1
0.71
-0.15
0.36
-0.2
-150 -100 -50
0
0 50 100 150 200 250
Vpd (Vdc)
Standby Mode
The ENX can be used to force the power detector into a low-power standby mode. In this mode, the entire power
detector is powered-down. As ENX is deactivated, power is restored to all of the circuits. There is no memory of
previous conditions. Coming-out of stand-by, C_INT and C_OFS capacitors will require recharging, so if large capacitor
values have been chosen, the wake-up time will be lengthened.
DC Offset Compensation Loop
Internal DC offsets, which are input signal dependant, require continuous cancellation. Offset cancellation is a critical
function needed for maintenance of measurement accuracy and sensitivity. The DC offset cancellation loop performs
this function, and its response is largely defined by the capacitance off. Setting DC offset cancellation, loop bandwidth
strives to strike a balance between offset cancellation accuracy, and loop response time. A larger value of C_OFS results
in a more precise offset cancellation, but at the expense of a slower offset cancellation response. A smaller value of
C_OFS tilts the performance trade-off towards a faster offset cancellation response. The optimal loop bandwidth setting
will allow internal offsets to be cancelled at a minimally acceptable speed.
12 - 150
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