HMC6001LP711E Datasheet, PDF (12/18 Pages) Hittite Microwave Corporation – WiGig Single Carrier Modulations

HMC6001LP711E
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MILLIMETERWAVE RECEIVER
57 - 64 GHz
Theory of Operation
An integrated frequency synthesizer creates a low-phase noise LO between 16.3 and 18.3 GHz. The step size of the
synthesizer equates to 540MHz steps at RF when used with 308.5714 MHz reference crystal (compatible with the
IEEE channels of the ISM band) or 500 MHz steps if used with a 285.714 MHz reference crystal.
A 57 to 64 GHz signal is received by an integrated low profile antenna which is connected to the single-ended LNA on
the IC. The LO is multiplied by three and mixed with the LNA output to downconvert to an 8 to 9.1 GHz sliding IF. An
integrated notch filter removes the image frequency. The IF signal is filtered and amplified with 17 dB of variable gain.
If the chip is configured for IQ baseband output, the IF signal is fed into a quadrature demodulator using the LO/2 to
downconvert to baseband. There are also options to use on-chip demodulators capabable of to demodulating AM/
FM/FSK/MSK waveforms. Contact Hittite application support for further guidance and application notes if interested
in these modes.
The phase noise and quadrature balance of the HMC6001LP711E is sufficient to demodulate up to 16QAM modulation
for high data rate operation.
There are no special power sequencing requirements for the HMC6001LP711E; all voltages are to be applied
simultaneously.
Register Array Assignments and Serial Interface
The register arrays for both the receiver and transmitter are organized into 16 rows of 8 bits. Using the serial interface,
the arrays are written or read one row at a time as shown in Figure 25 and Figure 26, respectively. Figure 25 shows
the sequence of signals on the ENABLE, CLK, and DATA lines to write one 8-bit row of the register array. The ENABLE
line goes low, the first of 18 data bits (bit 0) is placed on the DATA line, and 2 ns or more after the DATA line stabilizes,
the CLK line goes high to clock in data bit 0. The DATA line should remain stable for at least 2 ns after the rising edge
of CLK.
The Rx IC will support a serial interface running up to several hundred MHz, and the interface is 1.2V CMOS levels.
A write operation requires 18 data bits and 18 clock pulses, as shown in Figure 26. The 18 data bits contain the 8-bit
register array row data (LSB is clocked in first), followed by the register array row address (ROW0 through ROW15,
000000 to 001111, LSB first), the Read/Write bit (set to 1 to write), and finally the Rx chip address 111, LSB first).
Note that the register array row address is 6 bits, but only four are used to designate 16 rows, the two MSBs are 0.
After the 18th clock pulse of the write operation, the ENABLE line returns high to load the register array on the IC; prior
to the rising edge of the ENABLE line, no data is written to the array. The CLK line should have stabilized in the low
state at least 2 ns prior to the rising edge of the ENABLE line.
Figure 25. Timing Diagram for writing a row of the Receiver Serial Interface
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