HD61202U Datasheet, PDF (9/33 Pages) Hitachi Semiconductor – Dot Matrix Liquid Crystal GraphicDisplay Column Driver

HD61202U
Function of Each Block
Interface Control
I/O Buffer: Data is transferred through 8 data bus lines (DB0–DB7).
DB7: MSB (most significant bit)
DB0: LSB (least significant bit)
Data can neither be input nor output unless $ to CS3 are in the active mode. Therefore, when $ to
CS3 are not in active mode it is useless to switch the signals of input terminals except #$% and ADC;
that is namely, the internal state is maintained and no instruction excutes. Besides, pay attention to #$%
and ADC which operate irrespectively of $ to CS3.
Register: Both input register and output register are provided to interface to an MPU whose speed is
different from that of internal operation. The selection of these registers depend on the combination of
R/W and D/I signals (Table 1).
1. Input register
The input register is used to store data temporarily before writing it into display data RAM.
The data from MPU is written into input register, then into display data RAM automatically by
internal operation. When $ to CS3 are in the active mode and D/I and R/W select the input register
as shown in Table 1, data is latched at the fall of the E signal.
2. Output register
The output register is used to store data temporarily that is read from display data RAM. To read out
the data from the output register, $ to CS3 should be in the active mode and both D/I and R/W
should be 1. With the read display data instruction, data stored in the output register is output while E
is high level. Then, at the fall of E, the display data at the indicated address is latched into the output
register and the address is increased by 1.
The contents in the output register are rewritten by the read display data instruction, but are held by
address set instruction, etc.
Therefore, the data of the specified address cannot be output with the read display data instruction
right after the address is set, but can be output at the second read of data. That is to say, one dummy
read is necessary. Figure 1 shows the MPU read timing.
Table 1 Register Selection
D/I
R/W
Operation
1
1
Reads data out of output register as internal operation (display data RAM →
output register)
1
0
Writes data into input register as internal operation (input register → display
data RAM)
0
1
Busy check. Read of status data.
0
0
Instruction
824