HD61202U Datasheet, PDF (8/33 Pages) Hitachi Semiconductor – Dot Matrix Liquid Crystal GraphicDisplay Column Driver

HD61202U
Terminal
Name
ADC
Number of
Terminals I/O
1
I
DB0–DB7 8
I/O
M
1
I
FRM
1
I
CL
1
I
ø1, ø2
2
I
Y1–Y64 64
O
Connected to Functions
V_CC/GND
Address control signal to determine the relation between
Y address of display RAM and terminals from which the
data is output.
ADC = High: Y1: H’0, Y64: H’63
ACD = Low: Y64: H’0, Y1: H’63
MPU
Data bus, three-state I/O common terminal.
HD61203U
Switch signal to convert liquid crystal drive waveform
into AC.
HD61203U
Display synchronous signal (frame signal).
Presets the 6-bit display line counter and synchronizes
the common signal with the frame timing when the FRM
signal becomes high.
HD61203U
Synchronous signal to latch display data. The rising CL
signal increments the display output address counter
and latches the display data.
HD61203U
2-phase clock signal for internal operation.
The ø1 and ø2 clocks are used to perform operations
(I/O of display data and execution of instructions) other
than display.
Liquid crystal
display
Liquid crystal display column (segment) drive output.
The outputs at these pins are at the light-on level when
the display RAM data is 1, and at the light-off level when
the display RAM data is 0.
Relation among output level, M, and display data (D) is
as follows:
M
1
0
D
Output
level
1010
V1 V3 V2 V4
#$%
1
I
MPU or
The following registers can be initialized by setting the
external CR #$% signal to low level.
1. On/off register 0 set (display off)
2. Display start line register line 0 set (displays from line
0)
After releasing reset, this condition can be changed only
by instruction.
NC
3
Open
Unused terminals. Don’t connect any lines to these
terminals.
Note: 1 corresponds to high level in positive logic.
823